Hardmask capping layer

ABSTRACT

A capping layer is formed over a hardmask layer to increase the etch resistance and overall performance of the hardmask layer. Embodiments include a hardmask layer formed over a substrate and a capping layer formed on the hardmask layer, the capping layer including a stack of at least two nanolayers.

RELATED APPLICATIONS

The present application is a Divisional application of application Ser. No. 13/590,556, filed on Aug. 21, 2012, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to hardmask layers. The present disclosure is particularly applicable to hardmask layers with capping layers for increased etch resistance.

BACKGROUND

Hardmasks are employed as etch masks for a variety of semiconductor manufacturing processes. Titanium nitride (TiN) hardmasks have been used, for example, for forming self-aligned vertical interconnect accesses (VIAs) (the simultaneous formation of a first layer metal and upper layer metal pattern and level (V0 and others) VIAs). However, TiN hardmask layers have poor etch resistance. The poor etch resistance prevents the hardmask layers from being used in processes related to, for example, trench first metal hardmask schemes, hardmask open schemes, and VIA double patterning schemes. Current conventional hardmask layers are also plagued by poor self-aligned VIA (SAV) performance as part of a dielectric etch. A marginal increase in the etch resistance of the hardmask layer will allow for critical functions like merged VIAs to be used with respect to new technology nodes. Merged VIAs will allow designers to fit more VIAs into a fixed space with no upgrade in lithography tool sets.

A need therefore exists for methodology enabling formation of hardmask layers with increased etch resistance and hardmask layer performance, and the resulting device.

SUMMARY

An aspect of the present disclosure is an efficient method for forming a capping layer of nanolayers on a hardmask layer.

Another aspect of the present disclosure is a hardmask layer having a capping layer of nanolayers thereon.

Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.

According to the present disclosure, some technical effects may be achieved in part by a method including: forming a hardmask layer over a substrate, and forming a capping layer on the hardmask layer, the capping layer including a stack of at least two nanolayers.

Aspects of the present disclosure include forming the capping layer and the hardmask layer to a total thickness of less than or equal to 40 nanometers (nm). An additional aspect includes forming the capping layer and the hardmask layer to a total thickness of 30 to 40 nm. Another aspect includes forming the capping layer to a thickness of 10 to 30 nm. Another aspect includes the capping layer being formed of nanolayers of silicon carbide (SiC), cubic boron nitride (c-BN), or turbostatic boron nitride (t-BN), or alternating nanolayers of SiC and silicon carbon nitride (SiCN), BN and TiN, or SiC and BN.

Another aspect of the present disclosure is a device including: a substrate, a hardmask layer over the substrate, and a capping layer on the hardmask layer, the capping layer including a stack of at least two nanolayers.

Aspects include a thickness of the capping layer and the hardmask layer being less than 40 nm. Another aspect includes a thickness of the capping layer and the hardmask layer being 30 to 40 nm. A further aspect includes a thickness of the capping layer being 10 to 30 nm. Yet another aspect includes the capping layer including nanolayers of SiC, c-BN, or t-BN, or alternating nanolayers of SiC and SiCN, BN and TiN, or SiC and BN.

Another aspect of the present disclosure includes: forming a TiN hardmask layer over a substrate, and forming a capping layer of at least two nanolayers on the TiN hardmask layer to a thickness of 10 to 30 nm, wherein a total thickness of the TiN hardmask layer and the capping layer ranges from 30 to 40 nm.

Another aspect includes the capping layer formed of nanolayers of SiC or t-BN, or alternating nanolayers of SiC and SiCN, BN and TiN, or SiC and BN.

Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

FIGS. 1 through 4 schematically illustrate a method for forming a capping layer on a hardmask layer, in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”

The present disclosure addresses and solves the current problem of poor etch resistance attendant upon etching through conventional hardmask layers. In accordance with embodiments of the present disclosure, a capping layer is formed over the hardmask layer to increase the overall performance of the hardmask layer with respect to etch resistance.

Methodology in accordance with embodiments of the present disclosure includes forming a hardmask layer over a substrate, and forming a capping layer on the hardmask layer, the capping layer including a stack of at least two nanolayers. The capping layer may include nanolayers of SiC, c-BN, or t-BN, or alternating nanolayers of SiC and SiCN, BN and TiN, or SiC and BN.

Adverting to FIG. 1, a method of forming a capping layer over a hardmask layer, in accordance with an exemplary embodiment, begins with a base layer 101. The base layer 101 may be any type of layer that may subsequently have a hardmask layer deposited on it or over it, such as an interlayer dielectric (ILD) or substrate in manufacturing a semiconductor device.

Next, a hardmask layer 201 may be formed over the base layer 101, as illustrated in FIG. 2. The hardmask layer 201 may be formed directly on the base layer 101, or may be formed on one or more additional layers between the hardmask layer 201 and the base layer 101, depending on the specifics of the process. The hardmask layer 201 may be formed of TiN. An additional hardmask layer of tetraethyl orthosilicate (TEOS) (not shown for illustrative convenience) may be included beneath the hardmask layer 201.

Adverting to FIG. 3, a capping layer 301 may be formed on the hardmask layer 201. The capping layer 301 may be formed to a thickness of 10 to 30 nm and may be formed via deposition. The combination of the capping layer 301 and the hardmask layer 201 may be formed to a thickness of less than or equal to 40 nm, such as 30 to 40 nm, as thicker hardmask and capping layers would undesirably increase the aspect ratio during later etching.

Further, as illustrated in FIG. 4, the capping layer 301 may be formed of at least two nanolayers 301 a and 301 b. The nanolayers 301 a and 301 b may be repeating nanolayers of only SiC, c-BN, t-BN, or a combination thereof. A capping layer of SiC may act as an etch stop layer over the TiN hardmask. Alternatively, the nanolayers 301 a and 301 b may include alternating nanolayers of SiC and SiCN, BN and TiN, or SiC and BN. SiC is harder than TiN, and, therefore, is a desirable capping material for the TiN. Further, the higher the carbon content, the better the capping layer acts as an NBlok layer. However, when SiC is one of two alternating nanolayers, the SiC should be nanolayer 301 b, separated from the TiN hardmask layer, as SiC tends to delaminate from TiN. For example, the nanolayer 301 a may be SiCN and the nanolayer 301 b may be SiC, and the nanolayers 301 a and 301 b may repeat to form a capping layer 301. Each one of the nanolayers 301 a and 301 b may be formed to a thickness of 0.5 to 10 nm, and the capping layer 301 may be formed to have 2 to 100 interfaces of the nanolayers 301 a and 301 b. By maximizing the number of nanolayers 301 a and 301 b (thereby increasing the number of interfaces) while minimizing the thickness of each nanolayer such that the thickness of the capping layer 301 remains constant, harder capping layers may be formed without increasing the residual stress. Rather, the residual stress is mitigated by the presence of the interfaces, which are believed to act as buffers and reduce the overall residual stress of the capping layer 301 leading to a capping layer 301 with a lower residual stress than any single nanolayer 301 a or 301 b that forms the capping layer 301.

The embodiments of the present disclosure achieve several technical effects, including improved etch resistance and increased the overall performance of a hardmask layer, thereby allowing the hardmask layer to be used in trench first metal hardmask schemes and double pattern VIA schemes. Embodiments of the present disclosure enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices.

In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein. 

What is claimed is:
 1. A device comprising: a substrate; a hardmask layer over the substrate; and a capping layer on the hardmask layer, the capping layer comprising a stack of at least two nanolayers.
 2. The device according to claim 1, wherein a thickness of the capping layer and the hardmask layer is less than 40 nm.
 3. The device according to claim 2, wherein a thickness of the capping layer and the hardmask layer is 30 to 40 nm.
 4. The device according to claim 1, wherein a thickness of the capping layer is 10 to 30 nm.
 5. The device according to claim 1, wherein the capping layer comprises nanolayers of silicon carbide (SiC).
 6. The device according to claim 1, wherein the capping layer comprises alternating nanolayers of SiC and silicon carbon nitride (SiCN).
 7. The device according to claim 1, wherein the capping layer comprises nanolayers of turbostatic boron nitride (t-BN), cubic boron nitride (c-BN), or a combination thereof.
 8. The device according to claim 1, wherein the capping layer comprises alternating nanolayers of BN and titanium nitride (TiN).
 9. The device according to claim 1, wherein the capping layer comprises alternating nanolayers of SiC and BN.
 10. A device comprising: a substrate; a hardmask layer over the substrate; and a capping layer on the hardmask layer, the capping layer comprising a stack of either: at least three alternating nanolayers of silicon carbide (SiC) and silicon carbon nitride (SiCN), at least three alternating nanolayers of boron nitride (BN) and titanium nitride (TiN), or at least three alternating nanolayers of SiC and BN.
 11. The device according to claim 10, wherein a thickness of the capping layer and the hardmask layer is less than 40 nm.
 12. The device according to claim 11, wherein a thickness of the capping layer and the hardmask layer is 30 to 40 nm.
 13. The device according to claim 10, wherein a thickness of the capping layer is 10 to 30 nm.
 14. A device comprising: a substrate; a titanium nitride (TiN) hardmask layer over the substrate; and a capping layer on the TiN hardmask layer to a thickness of 10 to 30 nm, the capping layer comprises a stack of either: at least 20 alternating nanolayers of silicon carbide (SiC) and silicon carbon nitride (SiCN), at least 20 alternating nanolayers of boron nitride (BN) and titanium nitride (TiN), or at least 20 alternating nanolayers of SiC and BN, wherein a total thickness of the TiN hardmask layer and the capping layer ranges from 30 to 40 nm.
 15. A device comprising: a titanium nitride (TiN) hardmask layer; and a capping layer on the TiN hardmask layer, the capping layer comprises a stack of either: alternating nanolayers of silicon carbide (SiC) and silicon carbon nitride (SiCN), alternating nanolayers of boron nitride (BN) and titanium nitride (TiN), or alternating nanolayers of SiC and BN.
 16. The device of claim 15, wherein the capping layer stack comprises at least 20 alternating layers.
 17. The device of claim 15, wherein the thickness of the capping layer ranges from 10 to 30 nm.
 18. The device of claim 15, wherein the TiN hardmask layer is disposed on an interlayer dielectric (ILD) or substrate.
 19. The device of claim 15, wherein each of the nanolayers is formed to a thickness of 0.5 to 10 nm. The device of claim 15, wherein a total thickness of the TiN hardmask layer and the capping layer ranges from 30 to 40 nm. 